Semiconductor devices are designed using what is known as simulation program with integrated circuits emphasis (SPICE) simulations. SPICE is a powerful computer program available under open source license as well as from a variety of commercial vendors. SPICE is typically used in integrated circuit (IC) and board level design to check the integrity of circuit designs and to predict circuit behavior. Given a particular design and values of a plurality of input parameters affecting the design and/or process, SPICE can accurately predict whether the resulting device will conform to a defined specification window, i.e., behave in an intended manner. Process variations in IC manufacturing include variations in fabrication as well as operational variations, such as flat-band voltage, oxide thickness, temperature, and stress.
Typical methodologies to determine if a device works over a technology window involve Monte Carlo simulations and corner run analysis for specific corners of the technology. Monte Carlo methods are a class of computational algorithms for simulating the behavior of various physical and mathematical systems, typically in a nondeterministic manner, e.g., by using random or pseudo-random numbers. Neither Monte Carlo nor corner run analyses can efficiently and economically assess performance of a device design to the technology window when the number of corners is large, e.g., thousands to millions of corners. A particular design having n process variables will have 2n corners. Each corner is a region of multi-dimensional space where all n process variables are at the extreme ends of their acceptable input range. Faces of the process space occur when some of the variables are at extreme ends of their acceptable input ranges and others are not.
It can be very difficult for design engineers to predict the reliability of a design, even when all the process variables are within the design tolerance. Generally, when a design fails despite being within design tolerances, it is because a combination of process variables are at an extreme of a permitted range, i.e., the process variables are at a corner or a face of the design space. Unfortunately, even with thousands SPICE runs, it is impossible to test, by simulation, all the corners to appropriately characterize the failure modes of the design. For example, with only 40 process variables, there are 240, or over a trillion corners. Furthermore, traditional methodology dictates that process variables be randomly selected with a distribution consistent with actual production or operation, typically a normal (bell curve) distribution. While this methodology is useful in predicting yield during an actual production run, it does not assist the designers in identifying specific areas of the design that contribute to the failure rate. This is because the normal distribution is center-weighted, which is not generally helpful in identifying failures. Typically, few if any of the simulations will occur near an actual design process face or corner even when millions of simulations are performed.
Therefore, there exists a need in the industry for a new methodology that will aid designers in identifying specific regions of the design space prone to failure, thereby enabling more reliable designs, higher yield rates, and lower overall cost.